Neural network based on Verilog HDL for fetal ECG extraction

Authors

  • Nirmal Adam Sait Department of Biomedical Engineering, SRM University, Chennai
  • M. Thangarajan Department of EEE, Sriram Engineering College, Chennai,
  • U. Snehalatha Department of Biomedical Engineering, SRM University, Chennai

DOI:

https://doi.org/10.7439/ijbr.v7i10.3665

Abstract

This work proposes a method used to extract fetal ECG signal. Fetal ECG is used to detect the proper functioning of fetus during the time of labour which helps the clinicians to diagnose the wellbeing of the fetus. In this paper, we used Verilog HDL to design a neural network for extraction of FECG (fetal ECG) from MECG (maternal ECG). XYLINX 3S500 model was used to implement the proposed signal. Fetal ECG was efficiently extracted with the help of an FPGA (field-programmable gate array) kit implementing Verilog HDL software.

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Author Biography

  • Nirmal Adam Sait, Department of Biomedical Engineering, SRM University, Chennai
    Assistant Prof

References

Khamene Ali and Negahdaripour Shahriar,

Matonia A., Jezewski J., Horoba K., Gacek A. and Labaj,

Michel Haritopoulos, C

Hasan M. A., Ibrahimy M. I. And Reaz M. B. I.,

Mamun Bin Ibne Reaz and Lee Sze Wei,

Lee J.,. Park K. L, and Lee K. J.,

Camps G., Martinez M., and Soria E.,

Azad K. A. K., Darus Z. M., and Ali M. A. M.,

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Published

2016-11-01

Issue

Vol. 7 No. 10 (2016): Oct

Section

Review Article

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How to Cite

1.
Neural network based on Verilog HDL for fetal ECG extraction. Int Jour of Biomed Res [Internet]. 2016 Nov. 1 [cited 2026 Mar. 29];7(10):698-701. Available from: https://ssjournals.co.in/index.php/ijbr/article/view/3665